1. Field of the Invention
The present invention relates to integrated circuits and more particularly to programmable logic arrays, herein referred to as PLA's.
2. History of the Prior Art
In recent years it has become more prevalent to implement logic functions using large scale monolithic integrated circuit techniques developed for more structured circuits such as shift registers and read only storage devices. These logic circuits are referred to as programmable logic arrays (PLA's).
A PLA is a structure consisting of an associative or search array coupled to a read array. The associative array performs logical AND operations on the inputs, while the read array combines the contents of the selected words so that the outputs are the result of logically ORing selected words. Since any combinational logic circuit can be written as a sum of products or as a product of sums, the first programmable array, the search or AND array, is designed to generate the product terms and the second programmable array, the read or OR array, is designed to generate the sum of the product terms.
In a conventional read array structure, the load devices are placed along the top and/or bottom of the array. In this arrangement of the load devices, the length of the drain diffusion, from the load device to the furthest physical gate, determines the capacitance and resistance of the diffusion, which in turn determines the speed and signal level variation of that particular output. In addition, the area required by the array, being determined by the number of outputs, remains fixed and large even if the number of gates is a minimum.
One exception to the prior art array structure is described in the publication "Programmable Logic Array With Increased Personalization Density" by D. A. Conrad et al, IBM Technical Disclosure Bulletin, Vol 19, No. 7, Dec., 1976, pages 2628-9, in which load devices associated with single gates may be placed along the side of the array.